AN IPV6 ROUTING TABLE LOOKUP ALGORITHM IN SOFTWARE AND ASIC BY DESIGNING A HIGH-LEVEL SYNTHESIS SYSTEM
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ABSTRACT
This dissertation has two contributions. The primary contribution is to present a trie based routing table lookup algorithm named CP-Trie. The secondary contribution is to present a high-level synthesis tool named C2RTL that can generate routing table lookup implementation in ASIC from C code. Routing table lookup is a key function of a router. It involves performing the longest prefix match (LPM). A router needs to perform a routing table lookup for each incoming packet. Highspeed routers generally implement routing table lookup in Software and ASIC (Application Specific Integrated Circuit). This dissertation describes a new routing table algorithm named CP-Trie that outperforms the state-of-the-art trie based routing table lookup algorithm in lookup speed while consuming slightly more memory. We evaluated our algorithms with real routing tables from RouteView project. Our experiments with real routing tables from core routers show that CPTrie achieves upto 1.43X lookup throughput on a general purpose CPU, but consumes 1.36-1.47X memory compared to the state-of-the-art solution. CP-Trie also outperforms the state-of-the-art solutions in ASIC. Implementing routing table lookup in ASIC is another challenge. The ASICs in high-speed routers are currently designed in a register transfer level (RTL) hardware description language (HDL) such as Verilog or VHDL. However, manually writing hardware logic is notoriously complicated and painful. This dissertation describes a high-level synthesis (HLS) tool named C2RTL that can generate Verilog RTL from C code. It takes a routing table lookup algorithm in C as an input and generates corresponding Verilog RTL code. We used C2RTL to generate the Verilog RTL implementation of CP-Trie. We then synthesized the generated RTL code with OpenROAD in a 1 GHz pipelined ASIC with a 45nm standard cell library. Our OpenROAD report shows that CP-Trie consumes 14% less power and 20.5% less area compared to the state-of-the-art solution in ASIC
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